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Patents 2017-04-13T14:11:20+00:00

Patents/Intellectual Property (IP)

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1. Dexter SM Tan, Benjamin Colombeau, Clark KK Ong, SH Yeong, CM Ng, KL Pey, “Method for fabricating semiconductor devices with shallow diffusion regions”, US Patent 8,101,487, January 24, 2012.

2. Tan Dexter, Pey Kin Leong, Yeong Sai Hooi, Chin Yoke King, Ong Kuang Kian, Ng Chee Mang, “Method for fabricating nano devices “, US Patent 8,338,280, 25 December 2012.

3. KK Ong, KL Pey, KJ Chui, Samudra Ganesh, YC Yeo, YF Chong, “Formation of strained Si channel and Si1-xGex source/drain structures using laser annealing”, US Patent 7,892,905, February 22, 2011.

4. KK Ong, YS Hooi, KL Pey, Chan Lap, YF Chong, “Method for forming a shallow junction region using defect engineering and laser annealingUS Patent 7,888,224, February 15, 2011.

5. YK Lim, CS Seet, TJ Lee, LC Hsia, KL Pey, “Integrated circuit system using dual damascene process”, US patent 7,253,097, August 7, 2007.

6. WH Lin, MS Zhou, KL Pey, and S Chooi, “Dual metal gate process: metals and their silicidesUS patent 7,005,716, Feb 28, 2006.

7. PS Lee, KL Pey, A See and L Chan, “Method and apparatus for performing nickel salicidation”, US patent 7,030,451, 18 April 2006.

8. W Lin, MS Zhou, KL Pey, and Chooi, “Methods to form dual metal gates by incorporating metals and their conductive oxides”, US patent no. 6,891,233, May 10, 2005.

9. PS Lee, KL Pey, A See and L Chan, “Method and apparatus for performing nickel salicidation”, US patent 6,890,854 , 10 May 2005.

10. W Lin, MS Zhou, KL Pey, S Chooi, “Methods to form dual metal gates by incorporating metals and their conductive oxides”, US patent 6,677,652, January 13, 2004.

11. W Lin, MS Zhou, KL Pey, and S Chooi, “Dual metal gate process: metals and their silicidesUS patent 6,750,519, June 15, 2004.

12. W Lin, MS Zhou, KL Pey, and Chooi, “Methods to form dual metal gates by incorporating metals and their conductive oxides”, US patent 6,835,989, Dec 28, 2004.

13. AYF Chong, R Cha and KL Pey, “Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure”, US patent no. 6,534,390, March 18, 2003.

14. W Lin, Z Dong, S Chooi and KL Pey, “Method to reduce variation in LDD series resistance”, US patent no. 6,534,388, March 18, 2003.

15. W Lin, KL Pey, MS Zhou, Z Dong and S Chooi, “Method of forming dual thickness gate dielectric structures via use of silicon nitride layers”, US patent 6,524,910, February 25, 2003.

16. CC Hu, KL Pey, YF Chong, WK Chim, P Neuzil and L Chan, “Incorporation of dielectric layer onto SThM tips for direct thermal analysis”, US Patent 6,566,650, 20 May 2003.

17. AYF Chong, KL Pey, A See,”Formation of silicided shallow junctions using implant through metal technology and laser annealing process”, US patent 6,624,489, September 23, 2003.

18. YF Chong, KL Pey and A See, “Formation of salicided ultra-shallow junctions using implant through metal technology and laser annealing process”, US patent 6,365,4446, April 2, 2002.

19. AYF Chong, R Cha, L Chan and KL Pey, “Method to reduce polysilicon depletion in MOS transistors”, US Patent 6,387,784, May 14, 2002.

20. YF Chong, KL Pey, and A See, “Activating source and drain junctions and extensions using a single laser anneal”, US patent  6,391,731, May 21, 2002.

21. CS Ho, KC Tee, KL Pey, G Karunasiri, SJ Chua, KH Lee and KH See, “Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions”, US patent 6,410,429, June 25, 2002.

22. W Lin, MS Zhou, KL Pey and S Chooi, “Methods to form dual metal gates by incorporating metals and their conductive oxides”, US patent 6,458,695, October 1, 2002 .

23. W Lin, KL Pey, MS Zhou and S Chooi, “Dual metal gate process: metals and their silicides”, US patent 6,475,908, November 5, 2002.

24. WL Tan, KL Pey, S Chooi, “Methods for effective nickel silicide formation”, US patent 6,339,021, January 15, 2002.

25. YF Chong, KL Pey, A See and TS Wee, “Method to form MOS transistors with shallow junctions using laser annealing”, US patent 6,335,253, January 1, 2002.

26. KL Pey, CS Ho and L Chan, “Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process “, US patent 6,180,501, Jan. 30, 2001.

27. CL Cha, CT Chua, KL Pey and L Chan, “Method to reduce compressive stress in the silicon substrate during silicidation”, US patent 6,284,610, September 4, 2001.

28. KL Pey, “Selective CVD TiSi2 deposition with TiSi2 liner”, US patent 6,316,811, November 13, 2001.

29. CW Lim, EH Lim, KL Pey and SY Siah, ” Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication“, US patent 6,271,133 August 7, 2001.

30. KL Pey, SY Siah and YM Lee, “Silicon nitride – TEOS oxide, salicide blocking layer for deep sub-micron devices“, US patent 6,025,267, Feb. 15, 2000.

31. CS Ho, RPG Karunasiri, SJ Chua, KL Pey and KH Lee, “CMOS gate architecture for integration of salicide process in sub-0.1m devices“, US patent 6,010,954, Jan. 4, 2000.

32. KL Pey, “Selective CVD TiSi2 deposition with TiSi2 liner”, US patent 6,110,811, August 29, 2000.

33. KL Pey and SY Siah “Salicide formation on narrow poly lines by pilling back of spacer“, US patent 6,153,485, Nov. 28, 2000.

34. CW Lim, KL Pey, SY Siah, EG Lim and Lap Chan “Ultra-low sheet resistance metal/poly-Si gate for deep sub-micron CMOS application“, US patent 6,093,628, Jul. 25, 2000.

35. EH Lim, KL Pey, H Wong & KH Lee, “In-line process monitoring using micro-Raman spectroscopy”, US patent 5,956,137, Sept. 21, 1999.

36. KL Pey, H Wong and L Chan, “Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance“, US patent 5,731,239, Mar. 24, 1998.

37. DSH Chan, KL Pey and JCH Phang, “Double reflection Cathodoluminescence detector with extremely high discrimination against backscattered electrons“, US patent 5,468,967, Nov. 21, 1995.

38. JCH. Phang, DSH Chan and KL Pey, “High efficiency cathodoluminescence detector with high discrimination against backscattered electrons“, US Patent 5,264,704, Nov 23, 1993.

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