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Conference 2018-02-12T12:26:45+00:00

Conference Proceedings

2018

1. A. Ranjan, N. Raghavan, S.J.O’ Shea, S. Mei, M. Bosman, K. Shubhakar and K.L. Pey, “Mechanism of soft and hard breakdown in hexagonal boron nitride 2D dielectrics”, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, (March 2018).

2. J.H. Lim, N. Raghavan, S. Mei, V. Naik, J.H. Kwon, K.H. Lee and K.L. Pey, “Area and pulse width dependence of bipolar TDDB in MgO STTRAM”, IEEE International Reliability Physics Symposium (IRPS)ORAL Presentation, (March 2018).

2017

1. K. L. Pey, A. Ranjan, S. Mei, N. Raghavan, K. Shubhakar, M. Bosman and S.J.O’ Shea, “Recent key developments in nanoscale reliability and failure analysis techniques for advanced nanoelectronics devices”, International Conference on Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film TransistorsINVITED  Talk, (2017).

2. L. Q. Luo, Y.J., Kong, F. Zhang, D. Shum, K. Shubhakar and K. L. Pey, “Automotive Functionality Demonstration of a 40nm Embedded High-Density 2.5V Self-Aligned Split-Gate NVM Macro”, International Memory Workshop (IMW)ORAL Presentation, (2017).

3. J. H. Lim, N. Raghavan, S. Mei, K. H. Lee, S. M. Noh, J. H. Kwon, E. Quek and K. L. Pey, “Asymmetric Dielectric breakdown behaviour in MgO based magnetic tunnel junctions ”, Insulating Films on Semiconductors (INFOS)ORAL Presentation, (2017).

4. A. Ranjan, N. Raghavan, B. Liu, S.J. O’Shea, K. Shubhakar, C.S. Lai and K.L. Pey, “Nanoscale investigations of soft breakdown events in few layered fluorinated graphene”, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, (2017).

5. S. Mei, N. Raghavan, M. Bosman and K.L. Pey, “Statistical basis and physical evidence for clustering model in FinFET degradation”, IEEE International Reliability Physics Symposium (IRPS)ORAL Presentation, (2017).

2016

1. S. Mei, N. Raghavan, M. Bosman, D. Linten, G. Groeseneken, N. Horiguchi and K.L. Pey, “New understanding of dielectric breakdown in advanced FinFET devices – physical, electrical, statistical and multiphysics study”, IEEE International Electron Devices Meeting (IEDM)ORAL Presentation (2016).

2. K.L. Pey, A. Ranjan, R. Thamankar, K. Shubhakar, N. Raghavan and S.J. O’Shea, “Observation of resistive switching by physical analysis techniques”, 5th International Symposium on Next-Generation Electronics (ISNE), Invited Talk, pp. 1-2, (2016).

3. K.L. Pey, R. Thamankar, S. Mei, M. Bosman, N. Raghavan and K. Shubhakar, “Understanding the switching mechanism in RRAM using in-situ TEM”, IEEE Silicon Nanoelectronics Workshop (SNW), Invited Talk, pp. 1-2, (2016).

4. K.L. Pey, A. Ranjan, R. Thamankar, K. Shubhakar, N. Raghavan and S.J. O’Shea, “Random telegraph noise study in HfO2 dielectric stacks using STM/CAFM: Analysis of local defects, degradation and breakdown”, IEEE International Nanoelectronics Conference (INEC), Invited Talk, pp. 1-2, (2016).

5. A. Ranjan, N. Raghavan, K. Shubhakar, R. Thamankar, J. Molina, S.J. O’Shea, M. Bosman and K.L. Pey, “CAFM based spectroscopy of stress-induced defects in HfO2 with experimental evidence of the clustering model and metastable vacancy defect state”, IEEE International Reliability Physics Symposium (IRPS), pp. 7A-4, (2016).

6. S. Mei, N. Raghavan, K. Shubhakar, M. Bosman and K.L. Pey, “Multiphysics based 3D percolation framework model for multi-stage degradation and breakdown in high-κ – interfacial layer stacks”, IEEE International Reliability Physics Symposium (IRPS), pp. 7A-2, (2016).

7. V.K. Ravikumar, G. Ranganathan, S.L. Phoa, J.M. Chin, K.L. Pey, K.W. Yang, W.L. Kok, L.S. Koh, “Implementing Time Resolved Soft Defect Localization using Pulse-at-will nanosecond Laser Diode”, 42nd International Symposium for Testing and Failure Analysis, pp 1-5, 2016.

8. L. Q. Luo, Z. Q. Teo, Y. J. Kong, F. X. Deng, J. Q. Liu, F. Zhang, X. S. Cai, K. M. Tan, K. Y. Lim, P. Khoo, S. M. Jung, S. Y. Siah, D. Shum, C. M. Wang, J. C. Xing, G. Y. Liu, Y. Diao, G. M. Lin, L. Tee, S. M. Lemke, P. Ghazavi, X. Liu, N. Do, K. L. Pey, K. Shubhakar, “Functionality Demonstration of a High-Density 2.5V Self-Aligned Split-Gate NVM Cell Embedded into 40nm CMOS Logic Process for Automotive Microcontrollers”, 8th International Memory Workshop (IMW), pp 1-4, 2016.

2015 – 2011

10. N. Raghavan, W. H. Liu, R. Thamankar, M. Bosman and K.L. Pey, “Understanding defect kinetics in ultra-thin dielectric logic and memory devices using random telegraph noise analysis”, 22ndInternational IEEE Symposium Physical and Failure Analysis of Integrated Circuits (IPFA), Invited Talkpp. 149-153, (2015).

11. Alok Ranjan, K. Shubhakar, N. Raghavan, R. Thamankar, M. Bosman, S. J. O’Shea, and K. L. Pey. “Localized Random Telegraphic Noise Study in HfO2 dielectric stacks using Scanning Tunneling Microscopy — Analysis of process and stress-induced traps”, 22nd International IEEE Symposium Physical and Failure Analysis of Integrated Circuits (IPFA), ORAL Presentation, pp. 458-462, (2015).

12. N. Raghavan, M. Bosman, and K. L. Pey, “Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer”, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, pp. 5A-2, (2015).

13. N. Raghavan, D. D. Frey, M. Bosman, and K. L. Pey, “Monte Carlo model of reset stochastics and failure rate estimation of read disturb mechanism in HfOx RRAM”, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, pp. 5B-2, (2015).

14. L. Q. Luo, D. X. Wang, F. Zhang, J. B. Tan, Y. T. Chow, Y. J. Kong, J. Y. Huang, Y. M. Liu, M. Oh, H. Balan, P. Khoo, C. Q. Chen, B. H. Liu, D. Shum, K. Shubhakar and K. L. Pey, “SRAM Vmin yield challenge in 40nm embedded NVM process”, IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), ORAL Presentation, pp 115-117, 2015.

15. N. Raghavan, K.L. Pey, D.D. Frey, M. Bosman, “Stochastic failure model for endurance degradation in vacancy modulated HfOx RRAM using the percolation cell framework“, 2014 IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, MY. 9.1-MY. 9.7, (2014).

16. N. Raghavan, K.L. Pey, D.D. Frey, M. Bosman, “Impact of ionic drift and vacancy defect passivation on TDDB statistics and lifetime enhancement of metal gate high-κ stacks“, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, 5B. 4.1-5B. 4.7, (2014).

17. K.L. Pey, N Raghavan, X Wu, M Bosman, XX Zhang, K Li, “Spatial correlation of conductive filaments for multiple switching cycles in CBRAM“, IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), ORAL Presentation, (2014).

18. N. Raghavan, K.L. Pey, K. Shubhakar, X. Wu, W.H. Liu and M. Bosman, “Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-κ gate dielectric stacks“, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, (2012).

19. W.H. Liu, K.L. Pey, N. Raghavan, X. Wu and M. Bosman, “Random telegraph noise reduction in metal gate high-κ stacks by bipolar switching and the performance boosting technique”, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, (2011).

20. K. Shubhakar, K.L. Pey, S.S. Kushvaha, S.J. O’Shea, M. Bosman, N. Raghavan, M. Kouda, K. Kakushima, Z.R. Wang, H.Y. Yu and H. Iwai, “Nanoscale physical study of polycrystalline high-κ gate dielectric stacks and proposed reliability enhancement techniques”, IEEE International Reliability Physics Symposium (IRPS), ORAL Presentation, (2011).

21. K.L. Pey, X. Wu, W.H. Liu, X. Li, N. Raghavan, K. Shubhakar and M. Bosman, “An overview of physical analysis of nanosize conductive path in ultra-thin SiON and high-κ gate dielectrics in nanoelectronic devices“, IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Invited Paper, pp.253-264, (2010).

22. K.L. Pey, N. Raghavan, X. Li, W.H. Liu, K. Shubhakar, X. Wu and M. Bosman, “New insight into TDDB and Post Breakdown Reliability of Novel High-κ Gate Dielectric Stacks”, IEEE International Reliability Physics Symposium (IRPS), Invited Paper, pp.354-363, (2010).

23. K.L. Pey, N. Raghavan, X. Wu, W.H. Liu, X. Li, M. Bosman, K. Shubhakar, Z.Z. Lwin, Y.N. Chen, H. Qin and T. Kauerauf, “Physical analysis of breakdown in high-κ / metal gate stacks using TEM/EELS and STM for reliability enhancement“, 17th International Symposium on Insulating Films on Semiconductors (INFOS), Invited Paper, (2011).

24. A.L. Danilyuk, D.B. Migas, M.A. Danilyuk, V.E. Borisenko, X. Wu, N. Raghavan and K.L. Pey, “Thermal formation of switching resistivity nanowires in hafnium dioxide”, Proceedings of the International Conference on Nanomeeting, pp.39-42, (2011).

2010 – 2006

27. Z. Z. Lwin, K. L. Pey, Y. N. Chen, P. K. Singh, and S. Mahapatra, “Charging and discharging characteristics of metal nanocrystals in degraded dielectric stacks,” in IEEE International Reliability Physics Symposium (IRPS), 2010, pp. 89-93.

28. N. Raghavan, K.L. Pey, W.H. Liu and X. Li, “New statistical model to decode the reliability and Weibull Slope of High-κ and Interfacial Layer in a Dual Layer Dielectric Stack”, IEEE International Reliability Physics Symposium (IRPS), Anaheim, California, pp.778-786, (2010).

29. XD. Wang, K.L. Pey, W.K. Choi, C.K.F. Ho, E. Fitzgerald, D. Antoniadis, “Arrayed Si/SiGe nanowire heterostructure formation via Au-catalyzed wet chemical etching method”, presented at ECS 214th meeting, Hawaii, USA, 12-17 Oct 2008 (Also ECS Trans. 16, 147 (2009)).

30. X. Li, G. Zhang, C. H. Tung and K. L. Pey, “Probing the electronic structures of defective oxides – an EELS approach”, IRPS2009, pp. 692-695, April 26 – 30, 2009, Montreal, Quebec, Canada.

31. V.L. Lo, K.L. Pey, R. Ranjan, C.H. Tung, J.R. Shih and Kenneth Wu, “Critical Gate Voltage and Digital Breakdown: Extending Post-Breakdown Reliability Margin in Ultrathin Gate Dielectric with Thickness < 1.6 nm”, IRPS2009, pp. 696-699, April 26 – 30, 2009, Montreal, Quebec, Canada.

32. Y. C. Ong, D. S. Ang, S. J. O’Shea, K. L. Pey, K. Kakushima, T. Kawanago, H. Iwai, C. H. Tung, “Real-time observation of trap generation by scanning tunneling microscopy and the correlation to high-κ gate stack breakdown”, IRPS2009, pp. 704-707, April 26 – 30, 2009, Montreal, Quebec, Canada.

33. Heryanto, Y.K. Lim, K.L. Pey, W. Liu, J.B. Tan, D.K. Sohn and L.C. Hsia, “The Influence Effects of Dielectric Slots on Copper/Low-k Interconnects Reliability”, IITC2009, pp. 92-94, May 2009, Japan.

34. X. Li, C. H. Tung and K. L. Pey, “Can a MOSFET Survive from Multiple Breakdowns?”, IEEE IPFA2009, pp. 153-157, 5-9 Jul 2009, Suzhou, China.

35. K.L. Pey, X. Li, R. Rakesh, V.L. Lo, “The chemistry of nanosize defective breakdown path in ultrathin SiON and high-k gate dielectric materials”, presented at the session on “Physics, chemistry and application of nanostructures” Nanomeeting, 25-29 May 2009, Belarus.

36. X. Li, K. L. Pey, V.L. Lo and R. Ranjan, “Impact of gate dielectric breakdown induced microstructural defects on transistor reliability”, Semiconductor Technology for Ultra Large Scale Integrated Circuits and Thin Film Transistors”, pp.11-25, 5-9 July, 2009, Xian, China.

37. K.L. Pey, “The chemistry of nanosize breakdown path in ultrathin SiON and high-k gate dielectrics of nanoelectronic devices”, IEEE EDS Mini-Colloquium on Nano-Scale Devices and Circuits, April 9 – 10 2009, Seoul National University, Korea.

38. K.L. Pey, “Physical analysis of dielectric breakdown in SiON and high-k gate dielectric materials”, IEEE EDS Mini-Colloquium on Nano-Scale Devices and Circuits, July 10-11 2009, Guangzhou, China.

39. K. S. Yew, Y. C. Ong, D. S. Ang, K. L. Pey, G. Bersuker, P. S. Lysaght and D. Heh, “Nanoscale Characterization of HfO2/SiOx Gate Stack Degradation by Scanning Tunneling Microscopy”, Accepted for presentation at SSDM 2009, Oct 2009.

40. W. H. Liu, K. L. Pey, X. Li, M. Bosman, “Observation of Switching Behaviors in Post-Breakdown Conduction in NiSi-gated Stacks”, accepted for presentation at IEDM’09.

41. N. Raghavan, K.L. Pey and X. Li, “Detection of high-κ and interfacial layer breakdown using the tunneling mechanism in a dual layer dielectric stack”, Applied Physics Letters, Vol. 95, 222903, (2009).

42. N. Raghavan, X. Wu, X. Li, W.H. Liu, V.L. Lo and K.L. Pey, “Post Breakdown Reliability Enhancement of ULSI Circuits with Novel Gate Dielectric Stacks”, IEEE International Symposium on Integrated Circuits (ISIC), Singapore, pp.505-513, (2009).

43. S. H. Yeong, B. Colombeau, C. H. Poon, K. R. C. Mok, A. See, F. Benistant. D. X. M. Tan, K. L. Pey, C. M. Ng, L. Chan and M. P. Srinivasan, “An extensive study on the boron junctions formed by optimized prior RTA/multiple-pulse flash lamp annealing (FLA) schemes: Junction Formation, Stability and Leakage”, ION IMPLANTATION TECHNOLOGY: 17th International Conference on Ion Implantation Technology. AIP Conference Proceedings, Volume 1066, pp. 47-50 (2008).

44. S. H. Yeong, D. X. M. Tan, B. Colombeau, L. Chan, K. L. Pey, J. P. Liu and M. P. Srinivasan, “Dopant diffusion and activation in SiGe/SiGeC layers and the incorporation of high energy silicon implantation with RTA and pulsed laser annealing”, 17th International Conference on Ion Implantation Technology, pg. 48, Monterey, California, USA, June 8-13, 2008.

45. D. X. M. Tan, K. L. Pey, B. Colombeau, K. K. Ong, C. M. Ng, S. H. Yeong, A. T. S. Wee, C. J. Liu and X. C. Wang, “Advanced Defect Engineering in Pre-Amorphized Si Substrate with Laser Pre-Irradiation optimization”, 17th International Conference on Ion Implantation Technology, pg. 28, Monterey, California, USA, June 8-13, 2008.

46. K.L. Pey, C.H. Tung, V. L. Lo, X. Li, “Nature of breakdown in ultrathin gate dielectrics”, The 2008 International Conference on Solid State and Integrated Circuit Technology (ICSICT 2008), October 20-23, 2008 in Beijing, China.

47. X. Li, C.H. Tung, K.L. Pey and V.L. Lo, “The Chemistry of gate dielectric breakdown”, Proceeding of IEEE 2008 IEDM, pp. 779-782 (2008 IEDM, 15-17 Dec 2008, San Francisco, USA).

48. Y. C. Ong, D. S. Ang, S. J. O’Shea, K. L. Pey, CH Tung, T. Kawanago, K. Kakushima, H. Iwai “Trap Generation in Sc2O3/La2O3 High-κ Gate Stack by Nanoscale Electrical Stress”, 2008 International Conference on Solid State Devices and Materials (SSDM2008), pp. 252-253, Sep 2008, Tsukuba, Japan.

49. Y. C. Ong, D. S. Ang, S. J. O’Shea, K. L. Pey, T. Kawanago, S. J. Wang, K. Kakushima, H. Iwai “Thermal Stability of High-κ Dielectrics – A Nanocharacterization Perspective”, 2008 International Conference on Solid State Devices and Materials (SSDM2008), pp. 336-337, Sep 2008, Tsukuba, Japan.

50. EJ Tan, KL Pey, N Singh, GQ Lo, DZ Chi, YK Chin, LJ Tang, “Erbium/Platinum silicided Gate-All-Around Silicon Nanowire Schottky Source/Drain MOSFETs”, presented at 2008 International Conference on Solid State Devices and Materials (SSDM2008), Sep 2008, Tsukuba, Japan.

51. Y.K. Chin, K.L. Pey, N. Singh, G.Q. Lo, L. Chan, L. H. Tan, and E. J. Tan, “Effect of Nickel Silicide Intrusion on Schottky Barrier Nanowire MOSFET Fabricated Using Top-down Technology”, presented at 2008 International Conference on Solid State Devices and Materials (SSDM2008), Sep 2008, Tsukuba, Japan.

52. V. L. Lo, K. L. Pey, C. H. Tung and D. S. Ang, “A Critical Gate Voltage Triggering Irreversible Gate Dielectric Degradation”, IEEE IRPS’07, pp. 576-577, 2007.

53. KL Pey, T A/L Selvarajoo, CH Tung, DS Ang and VL Lo, “Significance of breakdown location on post-breakdown transient and MOSFET degradation”, Presented at IRPS’07.

54. K. L. Pey, V. L. Lo, C. H. Tung, W. T. Lim, and D. S. Ang, “Influence of Oxide Breakdown Percolation Resistance on MOSFETs”, Presented at 211th Meeting of the Electrochemical Society 2007, 6-11 May 2007, Chicago, USA – Also Silicon Nitride, Silicon Dioxide and Emerging Dielectrics 9, pp. 431-447.

55. Y.K. Lim, K.L. Pey, P.S. Lee, Y.H. Lee, N.R. Kamat, J.B. Tan, Thomas Fu and L.C. Hsia, “Design for Manufacturability and its Role in Enhancing Stress Migration Reliability of Porous Ultra Low-k Copper Interconnects”, presented at IRPS’07.

56. H.P. Yu, K. L. Pey, W. K. Choi, D. A. Antoniadis, E. A. Fitzgerald, M. K. Dawood, K. Q. Ow and D. Z. Chi, “Full range workfunction tunning of MOSFETs using interfacial yttrium layer in fully germanided Ni gate”, presented at ECS 211th Meeting, Chicago, USA, 8-11 May 2007.

57. Y. Setiawan, P.S. Lee, S. Balakumar, K.L. Pey, X.C. Wang, ”Laser annealed Ni germanosilicide on SiGe substrates (Ge≈40%)”, presented at the MRS Spring Meeting 2007.
58. Y. Setiawan, P.S. Lee, K.L. Pey, X.C. Wang, B.L. Tan, “Formation of abrupt Ni(Pt) germanosilicide interface through laser induced self-limiting melting phenomenon in Si1-xGex/Si heterostructure”, presented at E-MRS 2007 Spring Meeting, Congress Center Strasbourg (France), May 28 to June 1 2007.

59. Y.K. Lim, J.B. Tan, K.L. Pey, E.C. Chua, Y.H. Yeo, Thomas Fu and L.C. Hsia, “Design for Manufacturability in Backend Reliability and Packaging of Nanoscale Technologies”, to be presented at IITC’07, USA.

60. E. Miranda, K.L. Pey, R. Ranjan, and C.H. Tung, “Analysis of the post-breakdown current in HfO2/TaN/TiN gate stack MOSFETs for low applied biases”, presented at INFOS’07.

61. E. Miranda, K.L. Pey, R. Ranjan, and C.H. Tung, “Analytic model for the post-breakdown current in HfO2/TaN/TiN gate stacks”, IEEE IPFA’07, 11-13 July, 2007, Bangalore, India, pp. 292-195.

62. N. Ranganathan, Liao Ebin, N. Balasubramanian, K.L. Pey and K. Prasad, “Development and characterization of silicon via tapering process for 3D System in Packaging application”, IEEE IPFA’07, 11-13 July, 2007, Bangalore, India, pp. 296-300.

63. V.L. Lo, S. Ashwin, K.L. Pey, C.H. Tung, “Comparison of Digital- and Analog-like Progressive Breakdown in nMOSFETs and pMOSFETs with Ultrathin Gate Oxide”, IEEE IPFA’07, 11-13 July, 2007, Bangalore, India, pp. 189-192.

64. E.J. Tan, K.L. Pey ,N. Singh, G.Q. Lo, D.Z. Chi, K. M. Hoe, P.S. Lee and, G. D. Cui, “Silicon Nanowire Schottky Barrier NMOS Transistors“, Presented at 2007 International Conference on Solid State Devices and Materials (SSDM2007) in Tsukuba, Japan. Session H5-4.

65. Y.C. Ong, S. J. O’Shea, D. S. Ang, K. L. Pey, T. Kawanago, K. Kakushima, H. Iwai, “Scanning Tunneling Microscopy on bi-layer gate dielectric stack of Sc2O3/La2O3/SiOx”, presented at ICNT’07, Sweden.

66. Y.C. Ong, D. S. Ang, S. J. O’Shea, K. L. Pey, T. Kawanago, K. Kakushima, H. Iwai,” Characterization of the Sc2O3/La2O3 High-k Gate Stack by STM”, presented at 2007 International Conference on Solid State Devices and Materials (SSDM2007) in Tsukuba, Japan.

67. V. L. Lo, K. L. Pey, C. H. Tung and X. Li, “Multiple Digital Breakdown and Its Consequence on Ultrathin Gate Dielectrics Reliability Prediction”, IEEE IEDM’07, pp. 497-500.

68. Chih Hang TUNG, Kin Leong Pey, Fu Qinrong, Bud Fox, “Atomic Scale Strain Measurement for Nanoelectronic Devices”, IEEE IPFA’07, 11-13 July, 2007, Bangalore, India, pp. 30-33.

69. Chee Lip Gan, Hoi Liong Leong, Carl V. Thompson, K.L. Pey, Hongyu Li, “Effects of Nanometer-Scale Surface Roughness and Applied Load on the Contact Resistance of Cu-Cu Bonded 3D ICs”, presented at MRS Fall meeting, November 2007 USA.

70. Y.K. Lim, J.B. Tan, K.L. Pey, E.C. Chua, Y.H. Yeo, Thomas Fu and L.C. Hsia, “Design for Manufacturability in Backend Reliability and Packaging of Nanoscale Technologies”, presented at IITC 2007, USA.

71. E.J. Tan, K.L. Pey, D.Z. Chi, P.S. Lee, and Y. Li, “Effect of TiN and TiN/Ti capping on the structural and electrical properties of rare earth silicides”, presented at ICMAT 2007, Singapore.

72. N. Ranganathan, Liao Ebin, N.Balasubramanian, K.Prasad and K.L. Pey, “Profile evolution of deep silicon tapered via for vertical system integration”, presented at ICMAT 2007, Singapore.

73. K.L. Pey, K.K. Ong, P. S. Lee, Y. Setiawan, X.C. Wang, A.T.S. Wee and G.C. Lim, “Formation of silicided hyper-shallow p+/n- junctions by pulsed laser annealing”, Presented at 212th Meeting of the Electrochemical Society 2007, Washington, DC, October 7-12 2007, Washington, DS, USA.

74. K.L. Pey, C.H. Tung, R. Ranjan, D.S. Ang, “Study of breakdown in nanoscale high-k gate stack using transmission electron microscopy,” invited paper to the 11th Workshop on Gate Stack Technology and Physics, Mishima, Japan, Feb 3-5, 2006.

75. R. Ranjan, K.L. Pey, C.H. Tung, D.S. Ang, L.J. Tang, T. Kauerauf, R. Degraeve, G. Groeseneken, S.De Gendt, and L.K. Bera, “Failure Defects Observed in Post-Breakdown High-k/Metal Gate Stack MOSFET,” IEEE IRPS, 590-594, 2006.

76. V. L. Lo, K. L. Pey, C. H. Tung and D. S. Ang, “Effects of Nano-scale Schottky Barrier of Conductor-like Breakdown Path on Progressive Breakdown in MOSFET,” IEEE IRPS, 619-620, 2006.

77. D. Z. Chi, R.T.P. Lee, M. Bouville, H. B. Yao, E. J. Tan and K. L. Pey, “Addressing materials and integration issues for silicide contact metallization in nano-scale CMOS devices”, Asia-Pacific Conference on Semiconducting Silicides : Science and Technology Towards Sustainable Optoelectronics (APAC-SILICIDE 2006), Kyoto University, Kyoto, Japan.

78. Y. Zheng, C. Troadec, K.L. Pey, A.T.S. Wee, S.J. O’Shea, N. Chandrasekhar, “BEEM Studies of Metal-HfO2-Si Structures”, International Conference on Nanoscience and Technology 2006, 30 Jul – 4 Aug 2006, Switzerland.

79. Setiawan, P.S. Lee, S. Balakumar, S.F. Choy, and K.L. Pey, “Micro-Raman Studies of a High Ge Concentration Si1-xGex Layer Condensed on Bulk Si and SOI Wafer”, International Conference on Nanoscience and Technology 2006, 30 Jul – 4 Aug 2006, Switzerland.

80. Y. Setiawan, P.S. Lee, K.L. Pey, X.C. Wang, G.C. Lim, F.L. Chow, “Laser annealed Ni(Ti) silicides formation”, 14th International Conference on Advanced Thermal Processing of Semiconductors – RTP2006, Page 223-227.

81. K.L. Pey, L.J. Jin, W. K. Choi, H. P. Yu, D. A. Antoniadis, E. A. Fitzgerald, D.Z. Chi and D. M. Isaacson, “Ni(alloy)-germanosilicide contact technology for Si1-xGex (x=0.20-0.5) junctions”, Proceeding of SSDM, pp. 338-339, 2006.

82. Y. Huang, K.L. Pey, D.Z. Chi, K.K. Ong, P.S. Lee, I.S. Goh, “Workfunction Adjustment Using Thin Metal Film (Ti, Pd) under FUSI Gate Electrode and Laser Annealing”, Proceeding of SSDM 2006, pp 220-221.

83. R Ranjan, KL Pey, CH Tung, DS Ang, LJ Tang, T Kauerauf, R Degraeve, G Groeseneken, S De Gendt, and LK Bera, “Substrate injection induced ultrafast degradation in HfO2/TaN/TiN gate stack MOSFET”, IEEE International Electron Device Meeting, 11-13 December 2006, Hilton San Francisco and Towers, San Francisco, CA, USA, pp. 759-762.

2005 – 2001

84. KL Pey, R. Ranjan, C.H. Tung, L.J. Tang, V.L. Lo, K.S. Lim, T. A/L Selvarajoo and D.S. Ang, “Breakdowns in high-k gate stacks of nano-scale CMOS devices”, INFOS’2005, Belgium, 22-24 June 2005.

85. KL Pey, “Pulsed laser annealing for the formation of ultra-shallow junctions for advanced semiconductor technology“, Workshop on Fundaments and Applications of Laser Processing for Highly Innovative (FLASH) MOS Technology, 21 Jan 2005, Rome, Italy.

86. VL Lo, KL Pey, CH Tung, DS Ang, LJ Tang, “Exponential dependence of percolation resistance on gate voltage and its impacts on progressive breakdown”, IEEE IRPS’05, pp 602-603.

87. YK Lim, R Arijit, KL Pey, CM Tan, CS Seet, and TJ Lee, “Stress Migration Reliability Assessment on Copper Gouging Via Structures”, IEEE IRPS’05, pp. 203-208.

88. K.L. Pey, K.K. Ong, P.S. Lee, A.T.S. Wee, X.C. Wang, Y.F. Chong, “Thermal Confinement of Advanced Semiconductor Substrates during Laser Annealing”, proceeding of the 4th Conference on Semiconductor Technology (ISTC2005), pp. 77-83, 15-17 March 2005, Shanghai, China.

89. W.T. Lim, V.L. Lo, K.L. Pey, D.S. Ang, C.H. Tung, “Study of dielectric-breakdown-induced dopant redistribution based on MOSFET diode I-V measurement”, IEEE IPFA’05, pp. 131-136.

90. Y. Setiawan, P.S. Lee, C.W. Tan, and K.L. Pey, ”Effect of Ti alloying in nickel silicide formation”, presented at ICMAT’05, Singapore, 4-8 July 2005.

91. K.K. Ong, K.L. Pey, P.S. Lee, A.T.S. Wee, Y.F. Chong, and X.C. Wang, “Dopant retention and electrical activation induced by laser annealing in boron implanted crystalline and preamorphized silicon”, presented at ICMAT’05, Singapore, 4-8 July 2005.

92. E.J. Tan, M. L. Kon, K. L. Pey, P.S. Lee, Y. W. Zhang, W. D. Wang, and D. Z. Chi, “Effects of Si(001) surface amorphization on ErSi2 thin film”, presented at ICMAT’05, Singapore, 4-8 July 2005.

93. L. J. Jin, K. L. Pey, W. K. Choi, D. A. Antoniadis, E. A. Fitzgerald and D. Z. Chi, “Electrical characterization of platinum and palladium effects in nickel monosilicide/n-Si Schottky contacts”, presented at ICMAT’05, Singapore, 4-8 July 2005.

94. K.L. Pey, C.H. Tung and L.J. Tang, “Characterization of microstructural and oxide damage of breakdown spot in MOSFETs using nanoanalytical techniques”, 208th Meeting of ECS, October 16-21, 2005, in Los Angeles, California, USA.

95. K.K. Ong, K.L. Pey, P.S. Lee, A.T.S. Wee, X.C. Wang, Y.F. Chong, L.H. Wong and C.C. Wong, “Enhanced dopant activation in strained-Si/Si1-XGeX substrate using non-melt laser annealing”, ECS Transactions, Volume 1, “Solid-State Joint General Poster Session”, 208th Meeting of ECS, October 16-21, 2005, in Los Angeles, California, USA.

96. Y. Setiawan, P.S. Lee, K.L. Pey, X.C. Wang and G.C. Lim, “Ni silicide formation in Ni(Ti)/Si using multiple pulsed laser annealing”, 208th Meeting of ECS, October 16-21, 2005, in Los Angeles, California, USA.

97. Choi, Z.-S., Chang, C.W., Lee, J.H., Gan, C.L., Thompson, C.V., Pey, K.L., Choi, W.K., “Multi-via electromigration test structures for identification and characterization of different failure mechanisms”, Materials Research Society Symposium Proceedings 863, pp. 271-276, 2005.

98. K.L. Pey, “Study of breakdown induced nanostructural damage in gate stacks”, Pre-INFOS 2005 – High-k Gate Stack Workshop, 21st Jun 2005, Leuven, Belgium.

99. K.L. Pey, “Study of breakdowns in high-k gate stacks of nano-scale MOSFETs”, Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (8th WIMNACT-Singapore), 2 July 2005, Singapore.

100. KL Pey, CH Tung and LJ Tang, “Nanoalaytical characterization of the breakdown spots in ultrathin gate dielectrics”, 2005 International Electron Device and Solid-State Circuit Conference (EDSSC’05), Hong Kong, December 19-21, 2005.

101. Y.K. Lim, K.L. Pey, J.B. Tan, T.J. Lee, D. Vigar, L.C. Hsia, Y.H. Lim, and N.R. Kamat, “Novel dielectric slots in Cu interconnctes for suppression stress-induced void failure” IEDM’05, pp. 187-190.

102. Das, A R. Saha, L J. Jin, K.L Pey, W K. Choi, D A. Antoniadis, E A. Fitzgerald, S Chattopadhyay, S Saha, C Bose, C K. Maiti, ” Studies on the Electrical Characteristics of Ni and NiPt-alloy Silicided Schottky Diodes”, URSI GA 2005.

103. L.J. Jin, K.L. Pey, W.K. Choi, E.A. Fitzgerald, D.A. Antoniadis, A.J. Pitera, M.L. Lee, and D. Z. Chi, “Study of Nickel (Platinum) (Pt at.% = 0, 5, 10) Germanosilicide Formation Using Micro-Raman Spectroscopy”, presented at MRS’04 Spring meeting, April 2004, USA.

104. C.W. Chang, C.L. Gan, C.V. Thompson, K.L. Pey, W.K. Choi, N. Hwang “Mortality Dependence of Cu Dual Damascene Interconnects on Adjacent Segment”, presented at MRS’04 Spring meeting, April 2004, USA.

105. J.Y.Y., Chaw, K. L., Pey, P.S., Lee, D.Z., Chi, J. P., Liu, “Study of Ni(Pt) germanosilicides formation on fully-strained”, presented at MRS’04 Spring meeting, April 2004, USA.

106. K.L. Pey, R Ranjan, C. H. Tung, L. J. Tang, W. H. Lin and M. K. Radhakrishnan, “Gate dielectric degradation mechanism associated with DBIE”, IEEE Proc. IRPS’04, pp. 117-121.

107. R Ranjan, KL Pey, LJ Tang, CH Tung, G Groeseneken, MK Radhakrishnan, B Kaczer, R Degraeve, S De Gendt, “A new breakdown failure mechanism in HfO2 gate dielectric”, IEEE Proc. IRPS’04, pp. 347-352.

108. F. Palumbo, S. Lombardo, K. L. Pey, L.J. Tang, C. H. Tung, W. H. Lin, M. K. Radhakrishnan and G. Falci, “Structure of the Breakdown Spot During Progressive Breakdown of Ultra-Thin Gate Oxides”, IEEE Proc. IRPS’04, pp. 583-584.

109. Y.K. Lim, Y. H. Lim, C. S. Seet, B. C. Zhang, K. L. Chok, K. H. See, T. J. Lee, L. C. Hsia, and K. L. Pey, “Stress-Induced Voiding in Multi-Level Copper/Low-k Interconnects”, presented at IEEE IRPS’04, 25-29 Apr 2004, Phoenix, USA.

110. K. K. Ong, K. L. Pey, P. S. Lee, K. L. Yeo, A. T. S. Wee, Y. F. Chong, and X. C. Wang, “Formation of ultra-shallow p+/n junctions in silicon-on-insulator (SOI) substrate using laser annealing”, presented at E-MRS 2004 Spring Meeting, May 24-28, 2004 – Strasbourg (France).

111. C.Y. Lu, C.H. Tung, K.L. Pey, “Microstructure evolution and breakdown mechanism studies in MOSFET with ultra thin gate dielectrics in nanometer technology era”, presented at ECS 206 meeting, 3-8 Oct 2004, Honolulu, Hawaii, USA.

112. S. Lombardo, F. Palumbo, J. H. Stathis, B. P. Linder, K.L. Pey, C. H. Tung, “Breakdown transients in ultra-thin gate oxynitrides”, presented at International Conference on IC Design and Technology, May 17-20, 2004, Austin, Texas, USA.

113. Y. Sun, K.L. Pey, C.H. Tung, S. Lombardo, F. Palumbo, L J Tang and M K Radhakrishnan,”Geometry Dependence of Gate Oxide Breakdown Evolution”, presented at IPFA’04, July 2004 Taiwan, pp. 57-60.

114. Y.K. Lim, Y.H. Lim, N. R. Kamat, A. See, T.J. Lee, and K.L. Pey, “Stress-Induced Voiding Beneath Vias with Wide Copper Metal Leads” presented at IPFA’04, July 2004 Taiwan, pp. 103-106.

115. R Ranjan, K L Pey, T A/L Selvarajoo, L J Tang, C H Tung and W H Lin, “Dielectric-Breakdown-Induced Epitaxy: A Universal Breakdown Defect In Ultrathin Gate Dielectrics”, presented at IPFA’04, July 2004 Taiwan, pp. 53-56.

116. K L Pey, C H Tung, L J Tang, R. Ranjan, M K Radhakrishnan, W H Lin, S. Lombardo and F. Palumbo, “Structural Analysis Of Breakdown In Ultrathin Gate Dielectrics Using Transmission Electron Microscopy”, Presented at IPFA’04, July 2004 Taiwan, pp. 11-16.

117. Z. -S. Choi , C. L. Gan , F. Wei, C. V. Thompson, J. H. Lee, K. L. Pey, and W. K. Choi, “Fatal Void Size Comparisons in Via-Below and Via-Above Cu Dual-Damascene Interconnects”, presented at MRS’04 Spring meeting, April 2004, USA.

118. F. Palumbo, G. Condorelli, S. Lombardo, K.L. Pey, C.H. Tung, L.J. Tang, “Structure of the Oxide Damage under Progressive Breakdown”, presented at WODIM’2004, Ireland.

119. R Ranjan, KL Pey, CH Tung, LJ Tang, G Groeseneken, LK Bera and S De Gendt, “A Comprehensive Model for Breakdown Mechanism in HfO2 High- Gate Stacks”, IEDM Tech. Dig., pp. 725 – 728, 2004.

120. KL Pey, VL Lo, CH Tung, W Chandra, LJ Tang, DS Ang, R Ranjan, “New insight into gate dielectric breakdown induced MOSFET degradation by novel percolation path resistance measurements”, IEDM Tech. Dig., pp. 717 – 720, 2004.

121. MK Radhakrishnan, KL Pey and CH Tung, “Device Reliability and Failure Mechanisms Related to Gate Dielectrics and Interconnects”, 17th VLSI design Conference, 7-9 January 2004, Bombay, India.

122. L. Gan, C. V. Thompson, K. L. Pey, W. K. Choi, C.W. Chang and Q Guo, “Effect of Current Direction on the Reliability of Multi-Terminal Cu Dual-Damascene Interconnect Trees”, IEEE IRPS’03 proceeding, pp. 594-595.

123. K. L. Pey, C. H. Tung, M. K. Radhakrishnan, L. J. Tang and W. H. Lin, “DIBE shape and hardness dependence on gate oxide breakdown location in MOSFET channel”, IEEE IRPS’03 proceeding, pp. 584-585.

124. L. Gan, C. V. Thompson, K. L. Pey, W. K. Choi, C. W. Chang and Q. Guo, “Experimental characterization of the reliability of multi-terminal dual-damascene copper interconnect trees”, Proceedings for the Materials Research Society Spring Meeting, vol. 766, p. 121-126, (2003).

125. C.W. Chong, C. L. Gan, C. V. Thompson, K. L. Pey and W. K. Choi, “Observation of Joule-Heating-Assisted Electromigration Failure Mechanisms for Dual Damascene Cu/SiO2 Interconnects”, IEEE IPFA’03 proceeding, pp. 69-74.

126. L.J. Tang, K. L. Pey, C. H. Tung, M. K. Radhakrishnan and W. H. Lin, “Gate dielectric breakdown induced microstructural damages in MOSFETs”, IEEE IPFA’03 proceeding, pp. 134-140.

127. M. Yeadon, R. Nath, C.B. Boothroyd, D.Z. Chi, K.L. Pey, W.K.Choi, E.A. Fitzgerald and D. Antoniadis, “Formation and Agglomeration of Nickel Monosilicide on Si and Si0.76Ge0.24 (001)”, Presented at MRS Fall 2003, USA.

128. Y.S. Li, P.S. Lee and K.L. Pey, “Ti/Co and Co/Ti silicidation of poly-Si capped poly-Si0.7Ge0.3 substrate”, presented at ICMAT, 8-12 Dec 2003, Singapore.

129. N.G. Toledo, P.S. Lee and K.L. Pey, “Characterization of junction leakage of Ti-capped Co- and Ni-silicided junctions”, presented at ICMAT, 8-12 Dec 2003, Singapore.

130. J. S. Pan, K. L. Pey, Z. Gong and W. D. Wang, “Growth and Characterization of Ta and TaNx as Diffusion Barrier in Cu/SiO2 Structures”, presented at ICMAT, 8-12 Dec 2003, Singapore.

131. L.J. Jin, K.L. Pey, W.K. Choi, E.A. Fitzgerald, D.A. Antoniadis, D.Z. Chi and C.H. Tung, “The interfacial reaction of Ni on (111) Ge & (100) Si”, presented at ICMAT, 8-12 Dec 2003, Singapore.

132. L.H. Wong, C.C. Wong, K.K. Ong, J.P. Liu, L. Chan, R.Rao, L. Liu, Z.X.Shen, K.L. Pey, “Thermal Stability of Strained Si/Si1-xGex Heterostructures for Advanced Microelectronics Devices”, presented at ICMAT, 8-12 Dec 2003, Singapore.

133. K.L. Pey, P.S. Lee, D. Mangelinck, “Ni(Pt) alloy silicidation on (100) Si and poly-silicon lines”, presented at ICMAT, 8-12 Dec 2003, Singapore.

134. M.K. Radhakrishnan, K.L. Pey, C.H. Tung, L.J. Tang and W.H. Lin, “Dielectric Breakdown Induced Epitaxy (DBIE) – A New Reliability Degradation Mechanism Associated with Ultrathin Gate Oxide Breakdown”, presented at ICMAT, 8-12 Dec 2003, Singapore.

135. KL Pey, “Ultrashallow Junction Formation for Sub-100nm Technologies Using Pulsed Excimer Laser”, Workshop and IEEE EDS Mini-colloquium on NAnometer CMOS Technology (3rd WIMNACT-Singapore), 15 Oct 2003, Singapore.

136. L. Gan, C. V. Thompson, K. L. Pey, W. K. Choi, F. Wei, Y. Bo and S. P. Hau-Riege, “Experimental characterization of the reliability of 3-terminal dual-damascene copper interconnect trees,” Mat. Res. Soc. Symp. Proc. vol. 716, B8.13.1-8.13.6, 2002.

137. Frank Wei, C. L. Gan, C. V. Thompson, J. J. Clement, S. P. Hau-Riege, K. L. Pey, W. K. Choi, H. L. Tay, B. Yu and M. K. Radhakrishnan, “Length effects on the reliability of dual-damascene cu interconnects,” Mat. Res. Soc. Symp. Proc. Vol. 716, B13.3.1-13.3.6, 2002.

138. C. L. Gan, F. Wei, C. V. Thompson, K. L. Pey, W. K. Choi, and B. Yu, ‘Consequence of preferential void formation at the Cu/Si3N4 interface on the multiple failure mechanisms of cu dual-damascene metallization’, IPFA2002 proceeding, pp. 124-128, 8-12 July 2002 (BEST paper awarded).

139. W. K. Choi, K. L. Pey, H. B. Zhao, T. Osipowicz and Z. X. Shen, “Nickel silicidation on polycrystalline silicon germanium films,” 8th International Conference on Electronic Materials, 10-14 June 2002, Xian, China.

140. K. L. Pey, C. H. Tung, M. K. Radhakrishnan, L. J. Tang and W. H. Lin, “Dielectric breakdown induced epitaxy in ultrathin gate oxide – A reliability concern,” IEDM Tech. Digest, pp. 163-166, 2002.

141. C. L. Gan, F. Wei, C. V. Thompson, K. L. Pey, W. K. Choi, S. P. Hau-Riege and B. Yu, “Contrasting Failure Characteristics of Different Levels of Cu Dual-Damascene Metallization”, 2002 European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Rimini, Italy.

142. YF Chong, KL Pey, ATS Wee, A See, CH Tung, R Gopalakrishnan and YF Lu, “Fundamental issues in rapid thermal annealing (RTP), spike RTA and excimer laser annealing (ELA) for the formation of shallow p+/n junction”, Proceedings of the 199th Meeting of Electrochemical Society, Vol. 2001-9, p. 311, 2001.

143. LW Chu, WK Chim and KL Pey, “Effect of transmission line pulsing of interconnects investigated using combined low-frequency noise and resistance measurements”, IPFA2001, 9-13 July 2001, Singapore.

144. WL Tan, KL Pey, SYM Chooi and JH Ye, “A comparative study of NiSi formation using a Ti capping layer and a thin middle Ti layer”, Mater. Res. Soc. Symp. Proc. 670, 2001.

145. P.S. Lee, D. Mangelinck, K.L. Pey, J. Ding, T. Osipowicz and L. Chan, “Enhanced stability of Ni monosilicide on MOSFETs poly-Si gate stack”, Presented at Materials for Advanced Metallization MAM 2001, 5th March-7th March, Sigtuna, Sweden, 2001.

146. PS Lee, D Mangelinck, KL Pey, J Ding, J Dai and A See, “Ni silicide formation on Si(100) and poly-Si with a presilicide N2+ implantation” Invited talk in the annual TMS meeting 2001, 12-16th February 2001, USA.

147. W.H. Lin, K.L. Pey, Z. Dong, S.Y.M. Chooi, M.S. Zhou, T.C. Ang, C.H. Ang, and W.S. Lau, “Ultrathin Nitride/Oxide Stack Gate Dielectric (14.9Å to 20.3 Å) for Sub-0.13m CMOS and Beyond”, Proceeding of the 2001 International Conference on Solid State Devices and Materials (SSDM), Tokyo, 2001, pp.160-161.

148. K. L. Pey, C. H. Tung, W. H. Lin and M. K. Radhakrishnan, ”Physical analysis of Ti-migration in 33 Å gate oxide breakdown,” IEEE IRPS2002 proceeding, pp. 210-215, April 4-8, 2002, Dallas Texas, USA.

149. MK Radhakrishnan, KL Pey, CH Tung, WH Lin and SH Ong, “Physical analysis of reliability degradation in sub-micron devices”, IEDM Tech, Digest, pp. 857-890, 2001.

2000 – 1996

150. CS Tan, WK Choi, LK Bera, KL Pey, DA Antoniadis, EA Fitzgerald, MT Currie, and CK Maiti, “N2O Rapid Thermal Oxidation of Strained Si/Relaxed SiGe Heterostructure grown by UHVCVD”, Proceeding of the International Conference on Computer, Communication and Devices, IIT Kharagpur, India, 14-16 December 2000.

151. S Chattopadhay, KL Pey, WK Choi and DZ Chi, DA Antoniadis and EA Fitzgerald, “Identification of deep level traps in a compositionally graded n-Si0.75Ge0.25 alloy using Ti Schottky diode”, International Conference on Communication, Computer and Devices (ICCCD), IIT India, pp. 123-126, 14-16 Dec 2000.

152. LT Koh, LW Chu, KL Pey and WK Chim, “Low-frequency noise measurement of copper damascene interconnects”, Presented at IITC, San Francisco, June 5-72000, USA.

153. YF Chong, KL Pey, ATS Wee, A See, C-H Tung, R Gopalakrishnan and YF Lu, “Application of Excimer Laser Annealing in the Formation of Ultra-shallow P+/n Junctions”, Proceedings of Advanced Microelectronic Processing Techniques, SPIE Vol. 4227, p. 124 (2000).

154. YL Teo, KL Pey, WK Chim, and YF Chong, “Study of Implanted Boron Distribution in P+n Structures Using Scanning Capacitance Microscopy” Proceedings of Advanced Microelectronic Processing Techniques, SPIE Vol. 4227, p. 174 (2000).

155. LW Chu, KL Pey, WK Chim, SK Low and E Er, ”Estimation of the effective void volume in deep-sub-micron aluminium interconnects using resistance-noise measurements”, Proceeding of SPIE, vol. 4229 (2000), pp. 157-167.

156. CS Tan, WK Choi, KL Pey, and LK Bera, “Electrical Characterization of Rapid Thermal Oxides grown on strained Si/relaxed SiGe Heterostructure”, Proceeding of the Electrical Engineering Conference 2000, University of Malaya, Malaysia, 8-9 August 2000.

157. HN Chua, KL Pey, SY Siah, EH Lim, and CS Ho, “Linewidth Dependence of Nano-Void Formation in Ti-Silicided BF2 Doped Polysilicon Lines”. Mat. Res. Soc. Symp. Proc. Vol. 564, pp. 91-95, 1999.

158. HN Chua, KL Pey, SY Siah, LY Ong, EH Lim, CL Gan, KH See, and CS Ho, “Impact of Voids in Ti-Salicided p+ PolySilicon Lines on TiSi2 Electrical Properties”, 7th International Symposium on the Physical And Failure Analysis of Integrated Circuits (IPFA 99), pp. 44-49, 1999.

159. EH Lim, SY Siah, CW Lim, YM Lee, FH Gn, R Sunderesan and KL Pey, “Degradation of pMOSFET series resistance due to Si implantation for Ti-salicide process”, SPIE, Microelectronic Device Technology, Santa Clara, USA, 21-22 Sept 1999.

160. CS Ho, KL Pey, CH Tung, KC Tee, S Prasad, D Saigal, JJL Tan, H Wong, KH Lee, T Ospowicz, SJ Chua and RPG Karunasiri, “Thermal studies on stress-induced void-like defects in epitaxial-CoSi2 formation”, Mat. Res. Soc. Symp. Proc. Vol. 564, pp. 109-116, 1999.

161. PS Lee, KL Pey, D Mangelinck, J Ding, T Osipowicz, CS Ho, Lap Chan, GL Chen, “characterization of Ni and Ni(Pt)-silicide formation on narrow polysilicon lines by Raman spectroscopy”, Oral presentation in the Materials Research and Society (MRS) Fall Meeting, 28th Nov-3rd Dec 1999, Boston, USA. Published in MRS Fall symposium proceeding vol. 591.

162. CS Ho, G Karunasiri, SJ Chua, KL Pey, SY Siah, KH Lee, and LH Chan, “Correlation of film thickness and deposition temperature with PAI and the scalability of Ti-salicide technology to sub-0.18m regime”, Proceeding for the 1st IEEE International Interconnect Technology Conference (IITC), pp. 193-195, 1998, USA.

163. K. L. Pey ” Application of Scanning Capacitance Microscopy to dopant profiling in ICs” Scanning Probe Microscope User Seminar 1998 jointly organized by PSB, Digital Instruments and Crest Technology, 15 May 1998, Productivity and Standard board, Singapore.

164. CS Ho, G Karunasiri, SJ Chua, KL Pey KH Lee, LH Chan and SY Siah “Implantation-induced degradation mechanism on PMOSFET series resistance for deep sub-micron titanium salicide process, Proceeding for the 15th VLSI Multi-level Interconnect Conference (VMIC), pp. 212-214, 1998.

165. CS Ho, G Karunasiri, SJ Chua, KL Pey, KH Lee, LH Chan and CH Tung “Process integration issues of a high-temperature Co/Ti salicide process for sub-quarter micron CMOS technology”, Proceeding for the 15th VLSI Multi-level Interconnect Conference (VMIC), pp. 218-220, 1998.

166. CW Lim, SK Lahiri, KH Lee, H Wong, KL Pey, SM Wong and L Chan, ”Impact of nitrogen ion-implantation on deep sub-micron SALICIDE process”, Microelectronic Device Technology, SPIE vol. 3212, 1997, pp. 151-161.

167. CS Ho, G Karunasiri, SJ Chua, KL Pey, H Wong, KH Lee, Y Tang, SM Wong and L Chan, “Effect of argon or nitrogen pre-amorphized implant on SALICIDE formation for deep-submicron CMOS technology”, Microlithographic Techniques in IC Fabrication, SPIE vol 3183, 1997, pp. 243-254.

168. CW Lim, KH Lee, KL Pey, H Gong, AJ Bourdillon and SK Lahiri, ”Robustness of self-aligned titanium silicide process: improvement in yield of salicided devices with APM cleaning step”, Proceeding for the 1st IEEE International Interconnect Technology Conference (IITC), pp. 187-189, 1998, USA.

169. CW Lim, H Gong, AJ Bourdillon, KH Lee, KL Pey, and SK Lahiri, ”Incorporating of APM-clean step in Ti-salicide process: a method to achieve high yield in silicided logic devices”, Proceeding for the 15th VLSI Multi-level Interconnect Conference (VMIC), pp. 278-280, 1998.

170. M Natarajan, TT Sheng, KL Pey, YP Lee and MK Radhakrishnan, “Analysis of dopant metrology using scanning capacitance microscopy and transmission electron microscopy as complimentary techniques”, 6th international symposium on the Physical & Failure Analysis of Integrated Circuits, 21-25 July 1997, Singapore, pp. 86-91.

171. CS Ho, G Karunasiri, SJ Chua, KL Pey, H Wong, KH Lee, and L Chan, “Integration of SALICIDE process for deep-submicron CMOS technology: Effect of nitrogen/argon-amorphized implant on SALICIDE formation”, VLSI Multilevel Interconnection Conference (VMIC), 10-12 June 1997, Santa Clara, California, pp. 396.

172. CW Lim, SK. Lahiri, K L Pey, K H Lee, H Wong, VN Chhagan, PS Tan, WH Chiu and L Chan, ”Study of spacer architecture and current leakage issue of sub-micron self-aligned silicide process”, 7th International Symposium on IC Technology, Systems & Applications 1997 (ISIC), Singapore, pp. 580-583.

173. CW Lim, SK Lahiri, H Wong, KL Pey, KH Lee, SM Wong and L Chan, ”Investigation of nitrogen ion-implantation into sub-micron CMOS devices fabrication process”, 7th International Symposium on IC Technology, Systems & Applications 1997 (ISIC), Singapore, pp. 588-592.

174. KL Pey, YE Strausser, AN Erickson, AJ Leslie, MTF Beh and TT Sheng, “Scanning capacitance microscopy analysis of DRAM trench capacitors”, Proc. of IEEE International workshop on Memory Technology, Design and Testing (MTDT), Singapore, August 13-14, 1996, pp. 79-85.

175. C Venkatesh, WK Chee, KL Pey, KH Tan and A. Trigg, “Surface integrity of polished infra-red optics and glass”, Proc. of the 11th annual meeting on the American Society for Precision Engineering, California, November 9-14, 1996, pp. 490-495.

176. LJ Liu and KL Pey, “HF wet etching of oxide after ion implantation”, Proceeding of the 1996 IEEE Hong Kong Electron Devices Meeting, June 29, 1996.

1995 – 1992

177. AJ Leslie, KL Pey, KS Sim, MTF Beh and GP Goh, “TEM sample preparation using FIB : Practical problems and artifacts”, ISTFA’95, Santa Clara, USA, 1-10 November 1995, pp. 353-362.

178. KL Pey, WF Wong, TH Chieng and LM Gan, “Application of low voltage electron microscopy to material and microelectronic analysis”, 3rd Institute of Material (E. Asia) conference on Recent advances in Material Analysis, 24th March 1995, Singapore.

179. KL Pey and AJ Leslie, “Focused Ion Beam Sample Preparation for high spatial resolution X-ray microanalysis”, IPFA’95, Singapore, November 27 – 1 December, pp. 40-48.

180. GHA Huan, SWE Wong, TAA Wee, KL Pey, R Gopalakrishnan and KL Tan, “Synthesis and properties of the Co0.8Cr0.1Pt0.1/Cr/Si Bilayer magnetic thin film”, ECASIA’95, Montreux, October 9 -13, 95, Switzerland, pp. 427-430.

181. CW Lim, MH Gao, WP Li and KL Pey, “Self-aligned silicide process with two-step rapid thermal processing”, Proc. of the 4th annual technical conference on Assembly, Packaging and IC Technology, 1995, Singapore, pp. 85-90.

182. KL Pey, Y Chen, W Qin and WK Chim, “Characterization of Al(Cu)/TaAl thin films used for thermal in jet devices using atomic force microscopy and transmission electron microscopy”, to be presented at the 5th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, Glasgow, Scotland, 4-7 Oct 1994.

183. KL Pey, DSH Chan and JCH Phang, “A numerical method for simulating cathodoluminescence contrast from localized defects,” Inst. Phys. Conf. Ser. no. 134, UK, 1993, pp.687-692.

184. WK Chim, DSH Chan, TS Low, JCH Phang, KS Sim and KL Pey, “Modeling techniques for the quantification of some electron beam induced phenomena,” Scanning Microscopy 92, 9-14 May 1992, Chicago, USA.

185. KL Pey, DSH Chan and JCH Phang, “Solid-state detector cathodoluminescence microscopy for inspection of III-V semiconductor compounds,” 5th Asia-Pacific Electron Microscopy Conference, 2-6 August 92, Beijing, China, pp.552-553.

186. KL Pey, DSH Chan and JCH Phang, “A simulation model for studying cathodoluminescence emissions,” In Computational Methods in Engineering Advances and Applications, edited by A.A.O. Tay and K.Y. Lam, World Scientific Publishing Co., pp. 821-826, 1992.

187. KL Pey, YY Liu, DSH Chan and JCH Phang, “Cathodoluminescence microscopy for inspection and characterization of optoelectronic materials,” In Proc. 2nd Scientific Conference of the Electron Microscopy Society Malaysia, pp. 3, Skudai, 1992.

188. KL Pey, PP Lim, DSH Chan, WK Chim and JCH Phang,” Application of monochromatic cathodoluminescence system to the failure analysis of light emitting diodes,” Proc. 3rd Int. Symp. Physical and Failure Analysis of Integrated Circuits, 11-15 November 91, Singapore, pp.109-114.

189. KL Pey, WK Chim, JCH Phang, DSH Chan and KY Chong,” SEM cathodoluminescence for failure analysis of optoelectronic devices,” Proc. 2nd Int. Symposium Physical and Failure Analysis of Integrated Circuits, 7-9 November 89, Singapore, pp.27-32.

190. KL Pey, DSH Chan and JCH Phang,” Application of cathodoluminescence in scanning electron microscope to investigation of optoelectronic devices,” Proc. 2nd Regional Symp. Optoelectronics, 27-28 November 89, Jakarta, Indonesia, pp. Moa-4/1-4.

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