Research

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#1 (Master of Engineering)

Project Title: Cognitive Sensor with Dual Mode of Operations in High Performance SPAD (Single Photon Avalanche Photo diode) Imager
Supervisor: Yeo Kiat Seng
Field of Interest: Semiconductors, Analog integrated circuit design and Advance optical sensor process technology, image algorithm and artificial intelligence

Abstract: SPAD sensor development has recently been a very much sought-after topic and new advances in CMOS process technology has enabled the realization of high pixel count 3D imagers using SPAD in the Geiger Mode of operations in a common terminology called Time of Flight (ToF). ToF is simply and optical arrangement whereby a laser light is synchronized with a SPAD sensor and the flight time of light photon from the sensor module to the object and its reflection is precisely measure yielding a depth of distance measurement. However, Avalanche Photodiodes can also be used in the Silicon Photo Multiplier mode in which the sensor can become a very high gain photon detector which is often used in medical imaging.

In this project, the student is required to study the details of both modes of operations of CMOS based SPADs and to investigate the possibility of using such photodiodes in the Geiger Mode as well as in the Silicon Photon Multiplier mode. The results of the device characteristics is the basis for the candidate to propose and develop suitable analog front-end circuitry whereby the sensor information obtained by each mode of operations can be digitalised and provided to the system host image processor for 3D object recognition – cognitive sensor.  A key focus of the front-end development will focus on very low power analog circuitry as well as low power digital processing of the ToF/ Photo-multiplier raw data before providing the information to upper layer applications and algorithms.

#2 (SUTD-CGU Dual Master Program in Nano–Electronic Engineering and Design (NEED))

Project title: Millimeter-wave Communication Systems for Low-power Applications
Supervisor: Yeo Kiat Seng
Co-supervisor: Tan Cher Ming, Chang Gung University (https://en.wikipedia.org/wiki/Chang_Gung_University)
Field of Interest: Semiconductors, RF/mm-wave integrated circuit design and Transceivers

Abstract: A high data-rate millimetre-wave (MMW) wireless communication system for low-power applications is proposed in this PhD research. The system is developed based on a system-on-chip (SoC) MMW transceiver with a Field Programmable Gate Array (FPGA) platform working as a baseband processor and medium access control (MAC) layer. The proposed design focuses on Gigabits-per-second (Gbps) outdoor point-to-point data transfer application for long distance communication. It will provide a full-duplex Gigabit Ethernet interface for the user to access the system. The project can be separated into background study, RF/MMW channel & link budget estimation, system architecture construction, RF/MMW device measurement & non-ideal characteristic compensation, baseband synchronization, channel coding, MAC design, and prototyping.

In this project, the student will design and simulate a low-power MMW transceiver using EDA tools. Throughout this project, the student is expected to accomplish the following tasks:

• Literature review;
• Design of MMW transceiver;
• Paper publication for the work done.

Students who are interested in the area of IC design are strongly encouraged to apply.

Reading materials
[1].   T. S. Rappaport, W. Roh and K. Cheun, “Mobile’s millimeter-wave makeover”, IEEE spectr., vol 51, pp 34-58, 2014
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[14]. K. Ma, S. Mou, N. Mahalingam, Y.Wang, et al, “An integrated 60 GHz low power two-chip wireless system based on IEEE 802.11ad standard”, IEEE MTT-S Int. Microw. Symp, June 2014.
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[27]. N. Saito, et al., “A fully integrated 60-GHz CMOS transceiver chipset based on WiGig/IEEE 802.11ad with build-in self-calibration for mobile usage”, IEEE J. Solid-State Circuits, vol. 48, pp. 3146-3159, Dec. 2013.
[28]. K. Okada et al., “A Full four-channel 6.3-Gb/s 60-GHz CMOS transceiver with low-power analog and digital baseband circuit”, IEEE J. Solid-State Circuits, Vol. 48, no. 1, pp 46-65, Jan. 2013.
[29]. M. Boers, B. Afshar, I. Vassiliou, et al, “A 16 TX/16 RX 60 GHz 802.11ad chipset with single coaxial interface and polarization diversity”, IEEE J. Solid-State Circuits, vol.49, No. 12, Dec 2014.
[30]. A. Tomkins, A. Poon, E. Juntunen, et al., “A 60 GHz, 802.11ad /WiGig-compliant transceiver for infrastructure and mobile application in 130 nm SiGe BiCMOS”, IEEE J. Solid-State Circuits, vol.50, No. 10, October 2015.
[31]. R. Wu, Ryo Minami, Yuuki Tsukui, S. Kondo, T. Yamaguchi, et al, “64-QAM 60-GHz CMOS transceivers for 802.11ad/ay”,  IEEE J. Solid-State Circuits, vol.52, No. 11, November 2017.
[32]. T. Bharatha Kumar, “Temperature-Compensated dB-linear digitally controlled variable gain amplifier with DC offset cancellation”, IEEE Trans. Microw. Theory and Techn., vol. 61, no. 7, July. 2013.
[33]. T. Siriburanon et al. ”A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11ad,”  IEEE J. Solid-State Circuits, vol.51, no. 11, pp. 2560-2571, Nov. 2015.
[34]. K. Okada, “60 GHz WiGig frequency synthesizer using injection locked oscillator”, IEEE RFIC Symp. Dig Paper, Jun. 2012, pp. 76-79.
[35]. N. Mahalingam, Y. Wang, et al., “A 24 GHz low power low phase noise dual-mode PLL frequency synthesizer for 60 GHz application”, IEEE MTT-S Int. Microw. Symp. June. 2014.
[36]. W.  Ye, et al., “A 65 nm CMOS power amplifier with peak PAE above 18.9% from 57 to 66 GHz using synthesized transformer-based matching network”, IEEE Trans. Circuit and Syst. I, Reg. Papers, vol. 62, no.10, Oct. 2015.
[37]. J. H. Kim, J. H. Jeong, S. M. Kim, C.S.Park, and K. C. Lee, “prediction of error vector magnitude using AM/AM, AM/PM distortion of RF power amplifier for high order modulation OFDM system”, in IEEE MTT-S Int. Microw. Symp. Dig., Jun.2005, pp. 2017-2030.
[38]. R. W. Hamming, “Error detecting and error correcting codes”, The Bell System Technical Journal. April. 1950, Vol. 29, pp. 147-160,
[39]. Ranjan Bose, “Information Theory, Coding and Cryptography, 2Ed”, “Chap.5, Bose-Chaudhuri Hocquenghem (BCH) Codes “, Mcgraw Hill Education (India) Pte. Ltd., April 25, 2008.
[40].   J. Li, S. Lin, A.-G. Khaled, “LDPC: code design, construction, and unification”, Cambridge University, Cambridge CB2 8BS, United Kingdom, 2017.
[41].  “Information technology – Telecommunications and information exchange between systems – Local and metropolitan area networks – Specific requirements, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 3:  Enhancements for Very High Throughput in the 60 GHz Band”, IEEE Std 802.11ad-2012/Amd.3:2014(E).
[42].   Lin, Shu; Costello, Jr. Daniel J. “Error Control Coding:  Fundamentals and Applications”, New Jersey, NJ, Prentice-Hall, ISBN 0-13-283796-X, 1983.
[43].  James L. Massey, “shift-register synthesis and BCH decoding”, IEEE Trans. On Information Theory, VOL. IT-15, No.1 Jan 1969.
[44].  H. C. Chang, C. B. Shung, “New serial architecture for Berlekamp-Massey algorithm”, IEEE Trans. On Communication, Vol. 47, No. 4, April 1999.
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[46].    D. Mackay, R. Neal, “Near Shannon limit performance of low-density parity-check codes”, Electronics Letters, 32(18): pp. 1645-1646, August 1996.
[47].   Arikan E, “Channel polarization: A method for constructing capacity achieving codes for symmetric binary input memoryless channels”, IEEE Trans. on Information theory, pp. 3051-3073, 2008.
[48].    R. M Tanner, “A Recursive Approach to Low Complexity Codes”, IEEE Trans. on Inform. Theory. IT-27(5): pp. 533-547, Sep 1981.
[49].   M. M Jadhav, Ankit Pancholi, Dr. A. M Sapkal, “Analysis and implementation of soft decision decoding algorithm of LDPC”, IEEE International Journal of Engineering Trend and Technology(IJETT), Vol.4 Issue.6, June 2013
[50].   Rinu Jose, Ameenudeen Pe, “Analysis of hard decision and soft decision decoding algorithms of LDPC codes in AWGN”, IEEE International Advance Computing Conference (IACC), pp. 430-435, July 2015.
[51].   Saeid Daneshgar, Kaushik Dasgupta, “A 27.8Gb/s 11.5pJ/b 60GHz Transceiver in 28nm CMOS with Polarization MIMO”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2018.
[52].    Shinwon Kang, Chintan Thakkar, “A 40Gb/s 6pJ/b RX Baseband in 28nm CMOS for 60GHz Polarization MIMO”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2018.
[53]. K. Okada, N.Li, K. matsushita, et al, “A 60-GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE802.15.3c”,  IEEE J. Solid-State Circuits, vol.46, No. 12, Dec 2011.
[54]. T. Mitomo, Y. Tsutsumi, H.. Hoshino, et al., “A 2-Gb/s throughput CMOS transceiver chipset with in-package antenna for 60-GHz short-range wireless communication”, IEEE J. Solid-State Circuits, vol.47, No. 12, December 2012.
[55]. N. Saito, T. Takayuki, N. Shirakata, et al., “A  Fully Integrated 60-GHz CMOS transceiver chipset based on WiGig/IEEE 802.11ad with build-in  self calibration for mobile usage”, IEEE J. Solid-State Circuits, vol.48, No. 12, December 2013.
[56]. K. Okada,  R. Minami, Y. Tsukui, et al., “A 64-QAM 60GHz CMOS transceiver with 4 channel-bonding”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2014.
[57]. R. Wu, R. Minami, Y. Tsukui, et al., “64-QAM 60-GHz CMOS for IEEE 802.11ad/ay”, IEEE J. Solid-State Circuits, vol.52, No. 11, November 2017.
[58]. J. Pang, S. Maki, S. Kawai, et al., “A 128-QAM 60-GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance”, IEEE Intern. Solid-State Circuits Conference (ISSCC), Feb 2017.

#3 (SUTD-CGU Dual Master Program in Nano–Electronic Engineering and Design (NEED))

Project title: A 2.4GHz Ultra-Low-power Radio for Cognitive Cameras
Supervisor: Yeo Kiat Seng
Co-supervisor: Tan Cher Ming, Chang Gung University (https://en.wikipedia.org/wiki/Chang_Gung_University)
Field of Interest: Semiconductors, Wireless technology, Radio transceivers, Low-power design

Abstract: Most portable electrical devices today use battery as their power source which increases the weight, cost and form factor of these devices. This project will focus on advancing technologies to develop battery-less integrated circuits and systems. More specifically, an environmentally-friendly, reconfigurable radio frequency (RF) transceiver with an extremely energy-aware attribute will be designed and developed. In the past few decades, the fundamental system architecture of an RF transceiver has seen little change. While there are many innovative designs in the circuit block and subsystem level, there is practically no energy-aware system architecture that enables ultra-low-power consumption without compromising the performance. This is a revolutionary insight that has never been highlighted before. As power saving through sub-threshold design and energy-aware transceiver are cumulative, a theoretical power consumption reduction of 20 times over state-of-the-art RF transceiver is possible. This far exceeds the power reduction of each technology migration which only yields an average of 1.5 times power consumption reduction.

In this project, the student will design and simulate a 2.4GHz radio for ultra-low-power application using EDA tools. Throughout this project, the student is expected to accomplish the following tasks:

• Literature review;
• Design of a 2.4GHz radio;
• Paper publication for the work done.

Students who are interested in the area of IC design are strongly encouraged to apply.

Preliminary Experimental Results

Some preliminary investigations have been performed and the results are very encouraging. A high speed prescaler is an important block in an RF transceiver. It operates at the highest frequency and therefore consumes a large amount of power. As shown in Figure 1, our group has successfully designed and silicon verified a new low-power high-speed TSPC 2/3 prescaler. When compared with existing architectures, the proposed design is capable of achieving a power consumption reduction of at least 7 times [1,2] while operating at a high frequency of 4.5 GHz as shown in Table 1. Based on the insight gained from the analysis, we have totally eliminated the short-circuit power consumption of the prescaler at radio frequency. In addition, redundant operations in the existing prescaler are removed. Measurement results show that a divide-by-32/33 dual modulus prescaler implemented with this novel 2/3 prescaler is capable of operating up to 4.5 GHz with a power consumption of only 1.4mW.

Table 1: Comparisons of SUTD’s novel prescaler with existing prescalers

Specifications	SUTD’s novel prescaler	[1]	[2]
Process (μm)	0.18	0.25	0.18
Supply voltage (V)	1.8	2.5	1.8
Power Consumption for Divide-by-2 Operation at 4.5GHz (mW)	0.306	1.875	1.8
Power Consumption for Divide-by-3 Operation at 4.5GHz (mW)	0.461	2.178	1.89

References

1. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5 GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378-383, Feb. 2004.
2. P. Yu, M. A. Do, W. M. Lim, K. S. Yeo and J. G. Ma, “Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler,” IEEE Trans. on Microwave Theory and Techniques, vol. 54, no. 11, pp. 3828-3835, Nov. 2006.

List of Projects

NTU-CHRT Joint R & D Project Title: Characterization and Modeling of CMOS Devices

A-STAR Project Title: Software Defined Radio System-on-Chip, Pilot Phase

IHPC-NTU Project Title: Investigating The On-Wafer Coupling and Cross Talk Effects of CMOS RF ICs

A-STAR EHS 1 Project Title: Software Defined Radio System-on-Chip

A-STAR EHS 2   Project Title: An Ultra Low-Power RFIC Chip for Wireless & Communication Applications (Embedded & Hybrid Systems Phase II)

UESTC-NTU Joint R & D Project Title: System on Chip

EDB-NTU-MediaTek Project Title: Joint Industry Postgraduate (JIP) II Programme for MSc/ MEng students

Temasek Laboratories Project Title: Design of Low-Power High-Speed Error-Tolerant Digital Circuits for Application in Digital Signal Processing

NRF-Proof-of-concept (POC) grant (NRF2008NRF-POC001-178) Project Title: An Ultra Low-Power RF Transceiver Chip Towards a New Paradigm of Life Quality

EDB-NTU-Broadcom Singapore Pte Ltd Project Title: Semiconductor Specialist Manpower Programme

EDB-NTU-Infineon Technologies Asia Pacific Pte Ltd Project Title: Joint Industry Postgraduate Programme

EDB-NTU-Chartered Semiconductor Manufacturing Ltd Project Title: Semiconductor Specialist Manpower Programme

EDB-NTU-TUM-Texas Instruments Singapore (Pte) Ltd Project Title: Joint Industry Postgraduate II Programme

UESTC-NTU Joint R & D Project Title: System-on-chip: Realization of Software Radio

Joint Research Lab: Advanced RFIC@NTU Project Title: Joint Research Project with Advanced RFIC

EDB-NTU-MediaTek Project Title: Joint Industry Postgraduate (JIP) II Programme for PhD students

Ministry of Education MOE2008-T2-1-036 Project Title: Batteryless Flexible Transceiver for Biomedical Applications

EDB-NTU-Panasonic Semiconductor Asia Pte Ltd Project Title: Joint Industry Postgraduate II Programme for MEng and MSc students

NRF2010 NRF-POC001-001 Project Title: Rapid Design Verification Platform for Analog/ RF Circuits Beyond the Scale of 65nm and 60GHz ($250,000)

EDB-Marvell Asia Pte Ltd-NTU Joint R & D Project Title: Semiconductor Specialist Manpower Programme

EDB-NTU-Avago Technologies General IP (Singapore) Pte Ltd Project Title: Semiconductor Specialist Manpower Programme

EDB-NTU-Infineon Technologies Asia Pacific   Project Title: Joint Industry Postgraduate II Programme

EDB-NTU-Lantiq Asia Pacific Pte Ltd Project Title: Joint Industry Postgraduate II Programme

A-Star/ Exploit Technologies Pte Ltd Project Title: 60GHz RFIC Chipset Development (Radio Frequency Chipset)

EDB-Siliconcore Technology Singapore Pte Ltd-NTU Joint R & D Project Title: Joint Industry Postgraduate II Programme

NRF-Proof-of-concept (POC) grant NRF2011NRF-POC002-050 Project Title: Ion Camera: A Real-Time High-sensitivity and High-resolution ISFET-based Ion Detection System for Food and Drug Safety

60 GHz low power transceiver chip

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• Die photo

• Demoboard and antenna

• Key patents

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A 900MHz RFID Reader Chip with RC Calibration

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Selected chip photos