Dr. Jiang Yu


Dr. Jiang Yu received her B. S. in Microelectronics from Peking University, Beijing, China in 2005 and Ph.D. in Electrical and Computer Engineering from National University of Singapore (NUS), Singapore in 2009. Dr. Jiang is currently senior manager in Singapore University of Technology and Design (SUTD). She manages the projects covering broad areas which includes Artificial Intelligence (AI), Unmanned Systems, Information Systems as well as Engineering Systems. Before Joining SUTD, she was program leader and research scientist in A*STAR, Data Storage Institute (2011-2016) and worked on R & D for next generation Non-Volatile Memory (NVM) and neuromorphic chip development. She also served as co-mentor for PhD students on Resistive Random Access Memory (RRAM) during her work at A*STAR. Before joining A*STAR, she had worked in Unisantis Electronics to develop 3-Dimensional vertical nanowire Surround Gate Transistors (SGT), establishing process technologies and know-how for manufacturing and commercialization (2009-2011). She has published papers in top conferences such as IEDM, VLSI and several patents in semiconductor field.